Research

Paper

TESTING February 24, 2026

Rethinking Clause Management for CDCL SAT Solvers

Authors

Yalun Cai, Xindi Zhang, Zhengyuan Shi, Mengxia Tao, Qiang Xu

Abstract

Boolean Satisfiability (SAT) solving underpins a wide range of applications in Electronic Design Automation (EDA), particularly formal verification. However, this paper observes that the mainstream clause reduction heuristic in modern SAT solvers becomes ineffective in the critical domain of complex arithmetic circuit verification, such as multipliers. On these instances, the dominant Literal Block Distance (LBD) metric for measuring clause quality degrades into a simple value of clause length, without any perception of dynamic clause usage during solving.To address this issue, a novel clause reduction mechanism is proposed, which is entirely independent of LBD. Its core idea is to decouple and handle separately the two most fundamental characteristics of learnt clauses--inherent lineage and dynamic usage patterns--thereby avoiding the efficiency degradation caused by inappropriately mixing these properties. Experiments show that our method consistently improves mainstream solvers and achieves speedups of up to 5.74x on complex arithmetic circuit problems, while maintaining comparable performance on general-purpose benchmarks. These results challenge the prevailing LBD-centric clause quality metric for clause management.

Metadata

arXiv ID: 2602.20829
Provider: ARXIV
Primary Category: cs.LO
Published: 2026-02-24
Fetched: 2026-02-25 06:05

Related papers

Raw Data (Debug)
{
  "raw_xml": "<entry>\n    <id>http://arxiv.org/abs/2602.20829v1</id>\n    <title>Rethinking Clause Management for CDCL SAT Solvers</title>\n    <updated>2026-02-24T12:08:32Z</updated>\n    <link href='https://arxiv.org/abs/2602.20829v1' rel='alternate' type='text/html'/>\n    <link href='https://arxiv.org/pdf/2602.20829v1' rel='related' title='pdf' type='application/pdf'/>\n    <summary>Boolean Satisfiability (SAT) solving underpins a wide range of applications in Electronic Design Automation (EDA), particularly formal verification. However, this paper observes that the mainstream clause reduction heuristic in modern SAT solvers becomes ineffective in the critical domain of complex arithmetic circuit verification, such as multipliers. On these instances, the dominant Literal Block Distance (LBD) metric for measuring clause quality degrades into a simple value of clause length, without any perception of dynamic clause usage during solving.To address this issue, a novel clause reduction mechanism is proposed, which is entirely independent of LBD. Its core idea is to decouple and handle separately the two most fundamental characteristics of learnt clauses--inherent lineage and dynamic usage patterns--thereby avoiding the efficiency degradation caused by inappropriately mixing these properties. Experiments show that our method consistently improves mainstream solvers and achieves speedups of up to 5.74x on complex arithmetic circuit problems, while maintaining comparable performance on general-purpose benchmarks. These results challenge the prevailing LBD-centric clause quality metric for clause management.</summary>\n    <category scheme='http://arxiv.org/schemas/atom' term='cs.LO'/>\n    <published>2026-02-24T12:08:32Z</published>\n    <arxiv:primary_category term='cs.LO'/>\n    <author>\n      <name>Yalun Cai</name>\n    </author>\n    <author>\n      <name>Xindi Zhang</name>\n    </author>\n    <author>\n      <name>Zhengyuan Shi</name>\n    </author>\n    <author>\n      <name>Mengxia Tao</name>\n    </author>\n    <author>\n      <name>Qiang Xu</name>\n    </author>\n  </entry>"
}