Paper
Dynamically Reprogrammable Runtime Monitors for Bounded-time MTL
Authors
Chirantan Hebballi, Akash Poptani, Amrutha Benny, Rajshekar Kalayappan, Sandeep Chandran, Ramchandra Phawade
Abstract
A Runtime Verification (RV) framework that supports online, at-speed verification of properties that can change dynamically (during in-field operations) will benefit a large variety of applications. Several state-of-the-art RV frameworks propose to implement monitors on FPGAs. While this approach can support changes to the property being monitored during in-field operations, they struggle to keep pace with the system under verification which use high-performance processors. In this work, we propose a novel, reprogrammable monitor that is implemented using standard cells instead of FPGAs. This allows the monitor to be co-located with the system under verification (on the same die), and hence is amenable to at-speed monitoring of properties. Our proposed design consists of a programmable unit that implements five basic operations and a set of queue-update rules. We show that a composition of such programmable units faithfully implements discrete time, bounded MTL. We demonstrate through simulations that our proposed monitor can be reprogrammed (through its I/O pins) post deployment. A fairly large monitor which can support MTL formulae upto 16 atomic propositions occupies only 0.55 mm^2, while operating at a frequency of 1.25 GHz.
Metadata
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Raw Data (Debug)
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"raw_xml": "<entry>\n <id>http://arxiv.org/abs/2603.19851v1</id>\n <title>Dynamically Reprogrammable Runtime Monitors for Bounded-time MTL</title>\n <updated>2026-03-20T11:09:06Z</updated>\n <link href='https://arxiv.org/abs/2603.19851v1' rel='alternate' type='text/html'/>\n <link href='https://arxiv.org/pdf/2603.19851v1' rel='related' title='pdf' type='application/pdf'/>\n <summary>A Runtime Verification (RV) framework that supports online, at-speed verification of properties that can change dynamically (during in-field operations) will benefit a large variety of applications. Several state-of-the-art RV frameworks propose to implement monitors on FPGAs. While this approach can support changes to the property being monitored during in-field operations, they struggle to keep pace with the system under verification which use high-performance processors. In this work, we propose a novel, reprogrammable monitor that is implemented using standard cells instead of FPGAs. This allows the monitor to be co-located with the system under verification (on the same die), and hence is amenable to at-speed monitoring of properties. Our proposed design consists of a programmable unit that implements five basic operations and a set of queue-update rules. We show that a composition of such programmable units faithfully implements discrete time, bounded MTL. We demonstrate through simulations that our proposed monitor can be reprogrammed (through its I/O pins) post deployment. A fairly large monitor which can support MTL formulae upto 16 atomic propositions occupies only 0.55 mm^2, while operating at a frequency of 1.25 GHz.</summary>\n <category scheme='http://arxiv.org/schemas/atom' term='cs.LO'/>\n <category scheme='http://arxiv.org/schemas/atom' term='cs.FL'/>\n <published>2026-03-20T11:09:06Z</published>\n <arxiv:primary_category term='cs.LO'/>\n <author>\n <name>Chirantan Hebballi</name>\n </author>\n <author>\n <name>Akash Poptani</name>\n </author>\n <author>\n <name>Amrutha Benny</name>\n </author>\n <author>\n <name>Rajshekar Kalayappan</name>\n </author>\n <author>\n <name>Sandeep Chandran</name>\n </author>\n <author>\n <name>Ramchandra Phawade</name>\n </author>\n </entry>"
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