Paper
A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA
Authors
Neelesh Gupta, Peter Wang, Rajgopal Kannan, Viktor K. Prasanna
Abstract
Gated DeltaNet (GDN) is a linear attention mechanism that replaces the growing KV cache with a fixed-size recurrent state. Hybrid LLMs like Qwen3-Next use 75% GDN layers and achieve competitive accuracy to attention-only models. However, at batch-1, GDN decode is memory-bound on GPUs since the full recurrent state must be round-tripped through HBM every token. We show that this bottleneck is architectural, not algorithmic, as all subquadratic sequence models exhibit arithmetic intensities below 1 FLOP/B at decode time, making them more memory-bound than standard Transformers. We present an FPGA accelerator that eliminates this bottleneck by holding the full 2 MB recurrent state persistently in on-chip BRAM, converting the workload from memory-bound to compute-bound. Our design fuses the GDN recurrence into a five-phase pipelined datapath that performs only one read and one write pass over each state matrix per token, exploits Grouped Value Attention for paired-head parallelism, and overlaps preparation, computation, and output storage via dataflow pipelining. We explore four design points on an AMD Alveo U55C using Vitis HLS, varying head-level parallelism from 2 to 16 value-heads per iteration. Our fastest configuration achieves 63 $μ$s per token, 4.5$\times$ faster than the GPU reference on NVIDIA H100 PCIe. Post-implementation power analysis reports 9.96 W on-chip, yielding up to 60$\times$ greater energy efficiency per token decoded.
Metadata
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"raw_xml": "<entry>\n <id>http://arxiv.org/abs/2603.05931v1</id>\n <title>A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA</title>\n <updated>2026-03-06T06:03:38Z</updated>\n <link href='https://arxiv.org/abs/2603.05931v1' rel='alternate' type='text/html'/>\n <link href='https://arxiv.org/pdf/2603.05931v1' rel='related' title='pdf' type='application/pdf'/>\n <summary>Gated DeltaNet (GDN) is a linear attention mechanism that replaces the growing KV cache with a fixed-size recurrent state. Hybrid LLMs like Qwen3-Next use 75% GDN layers and achieve competitive accuracy to attention-only models. However, at batch-1, GDN decode is memory-bound on GPUs since the full recurrent state must be round-tripped through HBM every token. We show that this bottleneck is architectural, not algorithmic, as all subquadratic sequence models exhibit arithmetic intensities below 1 FLOP/B at decode time, making them more memory-bound than standard Transformers. We present an FPGA accelerator that eliminates this bottleneck by holding the full 2 MB recurrent state persistently in on-chip BRAM, converting the workload from memory-bound to compute-bound. Our design fuses the GDN recurrence into a five-phase pipelined datapath that performs only one read and one write pass over each state matrix per token, exploits Grouped Value Attention for paired-head parallelism, and overlaps preparation, computation, and output storage via dataflow pipelining. We explore four design points on an AMD Alveo U55C using Vitis HLS, varying head-level parallelism from 2 to 16 value-heads per iteration. Our fastest configuration achieves 63 $μ$s per token, 4.5$\\times$ faster than the GPU reference on NVIDIA H100 PCIe. Post-implementation power analysis reports 9.96 W on-chip, yielding up to 60$\\times$ greater energy efficiency per token decoded.</summary>\n <category scheme='http://arxiv.org/schemas/atom' term='cs.AR'/>\n <category scheme='http://arxiv.org/schemas/atom' term='cs.LG'/>\n <published>2026-03-06T06:03:38Z</published>\n <arxiv:comment>6 pages, 6 figures</arxiv:comment>\n <arxiv:primary_category term='cs.AR'/>\n <author>\n <name>Neelesh Gupta</name>\n </author>\n <author>\n <name>Peter Wang</name>\n </author>\n <author>\n <name>Rajgopal Kannan</name>\n </author>\n <author>\n <name>Viktor K. Prasanna</name>\n </author>\n </entry>"
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