Research

Paper

TESTING February 26, 2026

EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning

Authors

Guangyu Hu, Xiaofeng Zhou, Wei Zhang, Hongce Zhang

Abstract

Progress in hardware model checking depends critically on high-quality benchmarks. However, the community faces a significant benchmark gap: existing suites are limited in number, often distributed only in representations such as BTOR2 without access to the originating register-transfer-level (RTL) designs, and biased toward extreme difficulty where instances are either trivial or intractable. These limitations hinder rigorous evaluation of new verification techniques and encourage overfitting of solver heuristics to a narrow set of problems. To address this, we introduce EvolveGen, a framework for generating hardware model checking benchmarks by combining reinforcement learning (RL) with high-level synthesis (HLS). Our approach operates at an algorithmic level of abstraction in which an RL agent learns to construct computation graphs. By compiling these graphs under different synthesis directives, we produce pairs of functionally equivalent but structurally distinct hardware designs, inducing challenging model checking instances. Solver runtime is used as the reward signal, enabling the agent to autonomously discover and generate small-but-hard instances that expose solver-specific weaknesses. Experiments show that EvolveGen efficiently creates a diverse benchmark set in standard formats (e.g., AIGER and BTOR2) and effectively reveals performance bottlenecks in state-of-the-art model checkers.

Metadata

arXiv ID: 2602.22609
Provider: ARXIV
Primary Category: cs.AR
Published: 2026-02-26
Fetched: 2026-02-27 04:35

Related papers

Raw Data (Debug)
{
  "raw_xml": "<entry>\n    <id>http://arxiv.org/abs/2602.22609v1</id>\n    <title>EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning</title>\n    <updated>2026-02-26T04:32:07Z</updated>\n    <link href='https://arxiv.org/abs/2602.22609v1' rel='alternate' type='text/html'/>\n    <link href='https://arxiv.org/pdf/2602.22609v1' rel='related' title='pdf' type='application/pdf'/>\n    <summary>Progress in hardware model checking depends critically on high-quality benchmarks. However, the community faces a significant benchmark gap: existing suites are limited in number, often distributed only in representations such as BTOR2 without access to the originating register-transfer-level (RTL) designs, and biased toward extreme difficulty where instances are either trivial or intractable. These limitations hinder rigorous evaluation of new verification techniques and encourage overfitting of solver heuristics to a narrow set of problems. To address this, we introduce EvolveGen, a framework for generating hardware model checking benchmarks by combining reinforcement learning (RL) with high-level synthesis (HLS). Our approach operates at an algorithmic level of abstraction in which an RL agent learns to construct computation graphs. By compiling these graphs under different synthesis directives, we produce pairs of functionally equivalent but structurally distinct hardware designs, inducing challenging model checking instances. Solver runtime is used as the reward signal, enabling the agent to autonomously discover and generate small-but-hard instances that expose solver-specific weaknesses. Experiments show that EvolveGen efficiently creates a diverse benchmark set in standard formats (e.g., AIGER and BTOR2) and effectively reveals performance bottlenecks in state-of-the-art model checkers.</summary>\n    <category scheme='http://arxiv.org/schemas/atom' term='cs.AR'/>\n    <category scheme='http://arxiv.org/schemas/atom' term='cs.LG'/>\n    <published>2026-02-26T04:32:07Z</published>\n    <arxiv:comment>19 pages, 8 figures. Accepted by TACAS 2026</arxiv:comment>\n    <arxiv:primary_category term='cs.AR'/>\n    <author>\n      <name>Guangyu Hu</name>\n    </author>\n    <author>\n      <name>Xiaofeng Zhou</name>\n    </author>\n    <author>\n      <name>Wei Zhang</name>\n    </author>\n    <author>\n      <name>Hongce Zhang</name>\n    </author>\n  </entry>"
}